digital clock VHDL program

library ieee;
use ieee.std_logic_1164.all;
entity dclock is
port(rst,clk:in std_logic;hr,min,sec:inout integer);
end dclock;

architecture dclock of dclock is
begin
process(rst,clk)
begin
if rst ='1' then
hr<=0;min<=0;sec<=0;
elsif(clk'event and clk='1') then
sec <= sec+1;
if (sec = 59) then
min <= min+1;sec <=0 ;
if (min = 59 and sec=59) then
hr <= hr+1;min <= 0;sec <= 0;
if (hr=23 and min=59 and sec=59) then
hr <= 0;min <= 0;sec <=0;
end if;
end if;
end if;
end if;
end process;
end dclock;