Synchronous Up-Down Counters

A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown below. Similar to an asynchronous up-down counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence.

An examination of the sequence table shows: for both the UP and DOWN sequences, Q0 toggles on each clock pulse. for the UP sequence, Q1 changes state on the next clock pulse when Q0=1. for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0. for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1. for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic connected as shown in the logic diagram above.

Synchronous Up-Down Counters

A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown below. Similar to an asynchronous up-down counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence.

An examination of the sequence table shows: for both the UP and DOWN sequences, Q0 toggles on each clock pulse. for the UP sequence, Q1 changes state on the next clock pulse when Q0=1. for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0. for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1. for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic connected as shown in the logic diagram above.

Asynchronous Up-Down Counters

In certain applications a counter must be able to count both up and down. The circuit below is a 3-bit up-down counter. It counts up or down depending on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter will count up.

When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are gated into the clock inputs of FF1 and FF2 respectively. If the flip-flops are initially reset to 0's, then the counter will go through the following sequence as input pulses are applied.

Notice that an asynchronous up-down counter is slower than an up counter or a down counter because of the additional propagation delay introduced by the NAND networks